1. Field of the Invention
This invention relates to Electrically Erasable Programmable Read Only Memory (EEPROM) and in particular to methods and circuits for erasing arrays of stacked gate memory cells.
2. Description of Related Art
Typical flash EEPROMs contain millions of memory cells arranged in rows and columns. FIG. 1 shows part of a prior art EEPROM array including a column of stacked gate memory cells 11-14. Stacked gate memory cells take several forms. For example, a stacked gate memory cell can be a single floating gate transistor or a combination of a select transistor and a floating gate transistor. Examples of how to make stacked gate memory cells are provided in U.S. Pat. No. 5,033,023 entitled "High Density EEPROM Cell and Process for Making the Cell" issued to Hsia, et al. which is incorporated herein by reference in its entirety.
Stacked gate memory cells are programmed, erased, or read by applying voltages to the terminals of the memory cell. For example, to read memory cell 11 in FIG. 1, bit line BL1 which connects to drain 11D may be precharged to about 1 volt while source line SL1 attached to source 11S is kept at 0 volts. (The terms source and drain are used herein to identify current carrying terminals of a memory cell, even though memory cells are not limited to single transistors.) A voltage of 5 volts is then applied to word line WL1 and therefore to control gate 11G, while all other word lines WL2-WL4 are kept at 0 volts. If the threshold voltage of memory cell 11 is low enough, for example less than 3 volts, memory cell 11 turns on and current flows from bit line BL1 through memory cell 11. If the threshold voltage of memory cell 11 is high, for example greater than 6 volts, memory cell 11 remains off. If all other memory cells attached to bit line BL1 (memory cells 12-14) remain off, no current flows in bit line BL1. The state of memory cell 11 is then read by sensing the voltage or current flow on bit line BL1.
Voltages applied to sources, drains, and control gates can also program or erase the memory cells. Programming or erasing changes the threshold voltages of memory cells by changing the amount of charge stored in floating gates. For a typical n-channel stacked gate memory cell, programming (raising the threshold voltage to a high level) is accomplished using hot electron injection from the drain junction, and erasing (lowering the threshold voltage to a low level) is accomplished using Fowler-Nordheim tunneling from the source junction to the floating gate through a thin tunnel oxide.
Flash EEPROM are typically initialized by simultaneously erasing all of the stacked gate memory cells. Information is then stored in the flash EEPROM by programming individual cells. Simultaneous erasure of memory cells, sometimes referred to as a block erase, can also be performed on a part of an EEPROM, for example on a number of rows in an array.
After a block erase, the stacked gate memory cells do not have exactly the same threshold voltage. Instead, there is a distribution of threshold voltages. Such distributions are unavoidable for many reasons. For example, perfect precision during fabrication can not be achieved. Each memory cell always has at least minor differences from the others which causes the threshold voltages of some memory cells to drop faster than the threshold voltages of other cells.
Cycles of programming and erasing the memory cells change memory cells and widen the distribution of threshold voltages. Because hot carriers (either holes or electrons) can be trapped in oxide layers, cells have some hysteresis or memory of past programming. After many erase-program cycles, a block erase creates a distribution of threshold voltages so large that some memory cells are over-erased or erratic-erased.
Over-erased memory cells are memory cells with threshold voltages low enough to interfere with reading or programming of cells in the array. During reading, for example, over-erased memory cells leak sufficient current to affect sensing from the attached bit lines. Referring again to FIG. 1, during reading of memory cell 11, 5 volts is applied to word line WL1 and bit line BL1, and 0 volts is applied to word lines WL2-WL4 and source 11S. If memory cell 12 is over-erased, the memory cell 12 turns on or leaks and causes a current on bit line BL1 regardless of whether memory cell 11 is programmed or erased.
Over-erased memory cells can also produce errors during programming of memory cells. A typical n-channel memory cell is programmed (set to have a threshold voltage of about 6 volts or higher) by holding the source at 0 volts, taking the drain (or attached bit line) to about 6.5 volts, and taking the control gate (or attached word line) above 12 volts for approximately 10 .mu.s. Leaky memory cells may lower the voltage on the attached bit line and affect programming speed. Also, the threshold voltages of over-erased cells may be too low to raise to the desired level above 6 volts in the 10 .mu.s programming time.
The lives of flash EEPROMs are limited because program-erase cycles widen the threshold voltage distribution so that when the cells with the highest threshold voltages are erased, the cells with the lowest threshold voltage are over-erased. The over-erased memory cells make flash EEPROMs inoperable. To extend flash EEPROM life, methods and structures are needed to keep the threshold voltage distributions narrow.